Intermec 073290-001 Datenblatt Seite 104

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Seitenansicht 103
Chapter 4 — Theory of Operation
CPU JTAG
TMS
TDI
TDO
TCK
GND
3.3V
51
10 6
15 11
FPGA JTAG
TMS
TDI
TDO
TCK
GND
3.3V
RESET
1
2
19
20
GND
GND
GND
GND
GND
GND
NC
CPU JTAG
NC
NC
RST
TDO
NC
TCK
TMS
TDI
MR*
3.3V
GND
GND
GND
I2C
SDA
SCK
GND
TARGET
SYSTEM
FLEX
PIC PROGRAMMER
To P1 on
target system
073048 JTAG Board and 073049 flex
Debug Board
J33, J34 and J35 are 3 high-density 40-pin SMT board-to-board
connectors providing debug board access to the CK30 system bus and
control signals. These connectors are not installed on production boards,
and so are not intended as a field debug facility, but could be soldered
onto a production board to help diagnose a field problem as a last resort.
The signal set brought out through these connectors includes:
SA_MD31:0 (data bus)
SA_MA25:0 (addr bus)
Control signals RD/WR*, WE*, OE*, PWE*, RESET_IN*, DQM3:0,
RDY
SCAN_DREQ, PCI_IRQ, SA_BREQ, SA_BGNT
SDRAM control signals SDCAS*, SDRAS*, SDCS0*, SDCKE
Clocks SDCLK, FPGA_CLK
Chip selects FPGA_CS*, FLASH_CS*, PCI/HCR_CS*
94 CK30 Handheld Computer Service Manual
Seitenansicht 103
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